This invention relates to a charge-coupled device (CCD) shift register.
It is known to use a CCD array as a serial-parallel-serial (SPS) analog shift register for high speed signal acquisition.
An SPS analog shift register comprises an input serial register, an output serial register, and a parallel register that connects the input serial register to the output serial register. The parallel register is composed of multiple segments, each comprising a serial register, extending between the input register and the output register. An input signal is sampled at an input diode of the SPS shift register and consecutive samples are shifted through the input register. When the input register is full, the samples are shifted into respective segments of the parallel register, emptying the input register. The input register is filled and emptied again, and as each group of samples is shifted into the parallel register the samples that were previously shifted into the parallel register are advanced by one step through the parallel register. Ultimately, each group of samples reaches the output register, and is shifted serially through the output register to an output node of the SPS shift register.
U.S. Pat. No. 4,725,748 issued Feb. 16, 1988 (Hayes, et al) discloses a two-channel SPS analog shift register using a four-phase CCD fabricated on a p-type silicon die having an n-type buried channel region The input signal is sampled at input diodes of the two channels respectively, by sampling clocks that are of the same frequency but are 180.degree. out of phase with each other, and the charge samples are applied to input registers of the two channels respectively. One of the channels has a lead-in section, which delays the samples taken at the input diode of that channel by one-half the sampling clock period. Therefore, each sample taken by the channel having the additional transfer electrodes enters the serial register of that channel at the same time that the next sample, which is taken by the other channel, enters the shift register of that other channel. Therefore, the two consecutive samples can be clocked through the respective channels simultaneously.
The effective sampling rate of the two-channel shift register shown in U.S. Pat. No. 4,725,748 is twice the transfer clock rate. The technique disclosed in U.S. Pat. No. 4,725,748 may be applied to a two-phase shift register. In the current state of the art, the maximum effective sampling rate that can be achieved using a two-channel shift register based on the teachings of U.S. Pat. No. 4,725,748 is about 500 Ms/s.